another blast from the past

[Anne & Lynn Wheeler]

From: wheeler @ sjrlvm1
Date: 3/10/80 08:08:43

they were looking at doing things on a chip. I don't know if it is
conflict or complement. Some of the people worked on Vamps and would
like to do CMS but I don't think thier chips are that large (yet?).
xxxxxx (who used to be at Cambridge) and yyyyyy (who was in
Burlington). Burlington is still a strategic MVS shop with no VM. They
may have to install at least one. Thier MVS is 9 meg (leaving 7 meg.),
and they have a Fortran design program exceeding that size. VM/CMS
could provide him 16 meg. less about 200k or so. zzzzzzz in defense of
POK said they are seriously looking at segment protect in the hardware
now. Several weeks ago a TSO product admin. called me about putting
the scheduler into MVS. They appear to be running scared. It seems
that they would like to avoid having salesman going into MVS accounts
and admit that MVS isn't the answer to everything (and by implecation
the IBM salesman was wrong) and now they will have to install VM for
interactive computing. Also heard that POK management tried to brow
beat DP marketing into giving equal billing to TSO (after the VM/CMS
is the interactive way to go).

--

Talked to both TSS and Amdahl people about UNIX. That may appear to be
a more realistic threat to VM/CMS. It would appear that not only do
most IBM'ers not know what is going on outside the company but a lot
don't even know what is going on outside of thier own Lab.

--

Something about two-pi. NCSS has 100 3200 machines out in the field
and two-pi has another 130. They are all at different EC levels and
nobody appears to have records of which ECs are on which machines.

--

I'll be getting machine readible copy of the VMSHARE data base and
hope to be putting it up on the HONE system, in addition to our
machine. I would like to have a VMSHARE userid (something like
TYMSHARE has) so that outside users can dial-up and look at the data
base. Hears some PSR say that putting a problem onto VMSHARE usually
takes a day or two for an answer instead of a month or better on
RETAIN. I would eventually like to get some sort of restricted VNET
dial-up to pick up incremental changes (currently plan on receiving
monthly tapes).

--

After the 4300 experience session, somebody from POK siad the user
benchmarks probably drove the final nails into the 3031's coffin.

--

Oh yes, I flew back to San Jose with two people from a TSO performance
group. I'm afraid that I brutilized them. Thier parting shot was that
CMS & TSO were in different divisions and that bot divisions have to
spend money on interactive computing. POK has to continue to spend
money on TSO since that is the only thing they have.

... snip ...

misc. terms:

VAMPS ... a project that i worked on about the same time i was working
on ecps, resource manager, etc. it was a 5-way SMP design with lots
of stuff moved into microcde. misc. past postings mentioning vamps
http://www.garlic.com/~lynn/subtopic.html#vamps

MVS had (16mbyte) application space constraint (kernel and other
system stuff occupying majority of every application address space)
... misc. recent postings
http://www.garlic.com/~lynn/2006b.html#25 Multiple address spaces
http://www.garlic.com/~lynn/2006b.html#26 Multiple address spaces
http://www.garlic.com/~lynn/2006b.html#28 Multiple address spaces
http://www.garlic.com/~lynn/2006b.html#32 Multiple address spaces
http://www.garlic.com/~lynn/2006b.html#34 Multiple address spaces
http://www.garlic.com/~lynn/2006b.html#36 Multiple address spaces

NCSS was the first spin-off of cp/67 and cambridge science center
offering commercial time-sharing service
http://www.garlic.com/~lynn/subtopic.html#timeshare

two-pi produced a entry-level 360 clone that NCSS marketed under
their own logo.

vmshare is computer conferencing provided by tymshare starting
in the mid-70s for discussing vm
http://vm.marist.edu/~vmshare/

hone is the internal online interactive system providing world-wide
support to sales, marketing and field people. in the late 70s all
the US hone datacenters were consolidated in cal. there were clones
of the system at numerous places around the world.
http://www.garlic.com/~lynn/subtopic.html#hone

there were several benchmarking activity comparing 4341 and 3031
(as well as clusters of 4341 and 3033). misc. past 4341/3031
benchmarking references:
http://www.garlic.com/~lynn/2000d.html#0 Is a VAX a mainframe?
http://www.garlic.com/~lynn/2000d.html#7 4341 was "Is a VAX a mainframe?"
http://www.garlic.com/~lynn/2001l.html#32 mainframe question
http://www.garlic.com/~lynn/2001m.html#15 departmental servers
http://www.garlic.com/~lynn/2002b.html#0 Microcode?
http://www.garlic.com/~lynn/2002d.html#7 IBM Mainframe at home
http://www.garlic.com/~lynn/2002f.html#8 Is AMD doing an Intel?
http://www.garlic.com/~lynn/2002i.html#7 CDC6600 - just how powerful a machine was it?
http://www.garlic.com/~lynn/2002i.html#19 CDC6600 - just how powerful a machine was it?
http://www.garlic.com/~lynn/2002i.html#22 CDC6600 - just how powerful a machine was it?
http://www.garlic.com/~lynn/2002i.html#37 IBM was: CDC6600 - just how powerful a machine was it?
http://www.garlic.com/~lynn/2002k.html#4 misc. old benchmarks (4331 & 11/750)
http://www.garlic.com/~lynn/2003.html#10 Mainframe System Programmer/Administrator market demand?
http://www.garlic.com/~lynn/2005m.html#25 IBM's mini computers--lack thereof
http://www.garlic.com/~lynn/2005q.html#30 HASP/ASP JES/JES2/JES3
http://www.garlic.com/~lynn/2005q.html#38 Intel strikes back with a parallel x86 design

[Anne & Lynn Wheeler]

Post by Anne & Lynn Wheeler
they were looking at doing things on a chip. I don't know if it is
conflict or complement. Some of the people worked on Vamps and would
like to do CMS but I don't think thier chips are that large (yet?).
xxxxxx (who used to be at Cambridge) and yyyyyy (who was in
Burlington). Burlington is still a strategic MVS shop with no VM.

ref:
http://www.garlic.com/~lynn/2006b.html#xx another blast from the past

note, i've been redacting names to protect the guility


From: wheeler at sjrlvm1
Date: 9/16/82 13:57:14
Subject: bounce lock

re: bounce lock; The VAMPS design had only one processer (at a time)
executing CP code ... all the other processors would be executing
virtual machines. CP processor would execute microcode dispatcher
instruction to add virtual machine to runnable list. CP would then see
if there was anymore work to do & then execute dispatch instruction.
Dispatch instruction would either pull 1st available virtual machine
off the dispatch queue & execute it or enter wait state. All the other
enginess, when not executing a virtual machine would sit idle waiting
for something to be placed on the dispatching queue. When a CP service
was required that could not be handled by the extended microcode
assist, control would attempt to enter CP. If there was already
processor in CP, this resulted in a CPEXBLOK being queued for the CP
processor and control transferring to execute another virtual machine
on the dispatch list. The microcode queuing of this CPEXBLOK would
cause a special interrupt in the CP processor to dequeue it.

VAMPS was effectively killed in Sept. of 1975. In Nov. of 1975, I
began adapting the VAMPS design to a non-microcode Lexington (168AP).
The concept of a CP processing interrupt, I replaced with the 'single
system lock' design. The innovation that I contributed to the single
system lock design, was that a processor requiring CP services that
were not equivalent to the extended microcode function (i.e. those
things that potentially required global resources) ... would go for the
single system lock ... rather than spinning on that lock ... like
other single system lock designs did ... it would "bounce" off the
lock, queue the CPEXBLOK and go off to the dispatcher to find another
virtual machine to execute.

From: wheeler at sjrlvm1
Date: 9/16/82 14:07:34
Subject: bounce lock

"bounce lock" .... My term for the design is a bounce lock reflecting
what happens in the processor executing the instruction (i.e. the
processor bounces off the system lock and goes looking for something
else to do). The development team eventually began to refer to it as a
"defer" lock ... reflecting their orientation as a process/tread
(rather processor) orientated system program ... i.e. the virtual
machine (or process) request was queued for latter execution.

I believe "defer" lock is an incorrect name since the single system
lock is a processor orientated function (i.e. it prevents a processor
from entering "protected" cp code). It does not directly affect the
state of the virtual machine ... My orientation when I created the
design was to solve a processor execution problem ... and therefor a
nomenclature orientation representing what the processor has to do ...
not what is happening in.

... snip ...

some VAMPS (& SMP) background. a lot of the stuff that i had
"fastpathed" in cp67 was targeted to microcode in VAMPS (interrupt
handling, dispatching, and some process specific stuff that didn't
affect global system resources).

in the translating VAMPS to a software implemention, a minimal amount
of kernel code was parallelized ... leaving the vast majority of
kernel code "protected" by the single kernel lock. the majority of
the code was not parallelized ... but high-performance, critical
parts of the kernel was parallelized somewhat drawing on experience
gained by doing ecps. the trade-off was to get nearly all of the
thruput from a highly parallelized kernel with only slightly more
work than doing a kernel spin-lock implementation (which was common
in the period).

one of the emails is specifically about the semantic appropriateness
referring to the single lock as a "bounce lock" (my original
nomenclature) or a "defer lock" (used later).

various collected postings mentioning vamps
http://www.garlic.com/~lynn/subtopic.html#bounce

note that charlie had done quite a bit of work at the science
center
http://www.garlic.com/~lynn/subtopic.html#545tech

on fine-grain locking and highly parallelized smp. that is where the
invention of compare&swap instruction came out of (mnemonic chosen
because CAS are charlie's initials).
http://www.garlic.com/~lynn/subtopic.html#smp