Discussion:
moving on
(too old to reply)
Anne & Lynn Wheeler
2006-12-27 23:44:02 UTC
Permalink
Dear VM Community,
After many years as a VM Systems Programmer and Manager, I'll be
leaving Interactive Data at the end of December to pursue other
interests. My thanks to those of you whom I've known throughout the
years and to all the VM Community for your support. I'd especially
like to thank the VM Developers whose talent, creativity, and
dedication make VM such a great system. The VM mainframe continues
to be a key component of Interactive Data's IT operation.
Very best wishes for a Happy Holiday season and a Peaceful New Year.
old email mentioning IDC from long ago and far away:

first two paragraphs somewhat related to this old email from 1973 and 1975
http://www.garlic.com/~lynn/2006v.html#36 Why these original FORTRAN quirks?
http://www.garlic.com/~lynn/2006w.html#7 Why these original FORTRAN quirks?
http://www.garlic.com/~lynn/2006w.html#8 Why these original FORTRAN quirks?

whole lot of posts about trying to get address location independent
executable images
http://www.garlic.com/~lynn/subtopic.html#adcon

being mapped from (CMS) paged mapped filesystem that I had original
implemented for cp67 and then ported to vm370
http://www.garlic.com/~lynn/subtopic.html#mmap

misc. posts about vm-based commercial time-sharing services
http://www.garlic.com/~lynn/subtopic.html#timeshare

and some additional topic drift, recent posts discussing mapping
objects to virtual address space
http://www.garlic.com/~lynn/2006w.html#17 Cache, TLB and OS
http://www.garlic.com/~lynn/2006x.html#26 Multiple mappings
http://www.garlic.com/~lynn/2006x.html#11 Multiple mappings

From: wheeler
Date: 03/26/79 07:52:36

For relocate shared segment support, a shared segment may appear
anywhere within a virtual machine's address space (it does not need to
be at the position specified in the VMABLOK). The way I handled it in
DMKVMA was to use the PTO pointers in the VMABLOK to check the shared
segments, rather than using the segment index number to displace into
the segment table and pick-up the STE.

One of the co-op students that helped me write the original shared
segment support for release 2 VM (included the sub-set that is now in
the product DCSS) is now with Interactive Data Corporation (IDC). They
have taken the idea and put a whole group on expanding the idea. They
now call it Floating segments (instead of relocating segments). They
have a modified assembler for generating adcon free code and are
working on the compilers. All this work they have done has greater
significance than they realize. It would greatly simplify conversion
to an increased address space size.

Customers appear to be ordering 4300s in large quantities. Single
outstanding problem is how to do centralized maintenance. For example
Univ. of Maine has 1 4341 and 8 4331s on order. They would like to do
without any tape drives at all on the 4331s and do all maintenance
over the network from the 4341. One thing they wanted to know, would
it be possible to load data from the CPU's floppy disk reader? They
would initially be willing to have one tape drive which they move
around as each of the 4331s are installed, but they would then like to
get rid of it after that and rely on the network. Several other
installations are starting to talk about going the same way (Univ. of
Maine is considered a small installation). This question of remote
mainenance may become very critical (possibly the most critical) for
installations talking about 20, 30, 40 or more CPUs all being serviced
from a central site. I would suggest that you find as many people as
possible to start looking at it and networking in general before the
next share. By comparison all the current activity with performance
optimization by customers can be minimized by just ordering additional
CPUs (if they can maintain them in a reasonable way).

... snip ...


with regard to the last paragraph ... misc recent posts on the subject of
distributed vm operation and large 43xx installations:
http://www.garlic.com/~lynn/2006x.html#18 The Future of CPUs: What's After Multi-Core?
http://www.garlic.com/~lynn/2006x.html#30 The Elements of Programming Style
http://www.garlic.com/~lynn/2006x.html#31 The Future of CPUs: What's After Multi-Core?
http://www.garlic.com/~lynn/2006y.html#5 The Future of CPUs: What's After Multi-Core?
http://www.garlic.com/~lynn/2006y.html#6 The Future of CPUs: What's After Multi-Core?
Anne & Lynn Wheeler
2006-12-28 04:15:46 UTC
Permalink
Post by Anne & Lynn Wheeler
Customers appear to be ordering 4300s in large quantities. Single
outstanding problem is how to do centralized maintenance. For example
Univ. of Maine has 1 4341 and 8 4331s on order. They would like to do
without any tape drives at all on the 4331s and do all maintenance
over the network from the 4341. One thing they wanted to know, would
it be possible to load data from the CPU's floppy disk reader? They
would initially be willing to have one tape drive which they move
around as each of the 4331s are installed, but they would then like to
get rid of it after that and rely on the network. Several other
installations are starting to talk about going the same way (Univ. of
Maine is considered a small installation). This question of remote
mainenance may become very critical (possibly the most critical) for
installations talking about 20, 30, 40 or more CPUs all being serviced
from a central site. I would suggest that you find as many people as
possible to start looking at it and networking in general before the
next share. By comparison all the current activity with performance
optimization by customers can be minimized by just ordering additional
CPUs (if they can maintain them in a reasonable way).
re:
http://www.garlic.com/~lynn/2006y.html#20 moving on
above includes email in the post dated 26mar79
http://www.garlic.com/~lynn/2006y.html#email790326

The 4341 tests were on an early endicott engineering machine
(delivered to disk test lab) that had some temporary patches that
slowed it down compared to what production machine would be.

Following email from 2/20/79 mention customer talking about wanting to
place an order for 70 such machines.

this old post
http://www.garlic.com/~lynn/2001m.html#15 Multics Nostalgia
includes email from 4apr79
http://www.garlic.com/~lynn/2001m.html#email790404

about air force data systems looking at 20 4341s ... but then six
months later, the order had been increased to 210 (fall79).

Other recent posts mentioning orders of large numbers of 43xx
machines
http://www.garlic.com/~lynn/2006p.html#34 "25th Anniversary of the Personal Computer"
http://www.garlic.com/~lynn/2006p.html#39 "25th Anniversary of the Personal Computer"
http://www.garlic.com/~lynn/2006p.html#40 "25th Anniversary of the Personal Computer"
http://www.garlic.com/~lynn/2006s.html#41 Ranking of non-IBM mainframe builders?
http://www.garlic.com/~lynn/2006v.html#11 What's a mainframe?
http://www.garlic.com/~lynn/2006v.html#19 Ranking of non-IBM mainframe builders?
http://www.garlic.com/~lynn/2006v.html#25 Ranking of non-IBM mainframe builders?
http://www.garlic.com/~lynn/2006x.html#18 The Future of CPUs: What's After Multi-Core?
http://www.garlic.com/~lynn/2006y.html#5 The Future of CPUs: What's After Multi-Core?

From: wheeler
Date: 02/12/79 13:01:01

Following are times for floating point fortran job running identical
CP&CMS (4341 does not have ECPS on)

158 3031 4341
Rain 45.64/47.42 | 37.03/37.77 | 36.21/37.57
Rain4 43.90/44.80 | 36.61/36.89 | 36.13/36.51

also times approx;
145 168 91
145 secs. 9.1 secs 6.77 secs

... snip ...


of course the following MVS 168-3 doesn't include the "capture
ratio" information ... some discussion in this post
http://www.garlic.com/~lynn/2006x.html#19 Ranking of non-IBM mainframe builders?

From: wheeler
Date: 02/12/79 21:36:29

Do you know if the STL VM 168s have (or don't have) the high speed
multiply feature?????

the 168-3 VM test number was taken from STLVM3

Following are times for floating point fortran job running identical
CP&CMS (4341 does not have ECPS on). Command was 'LOAD XXXX (START'
link-edit time included).

RAIN RAIN4

158 | 45.64/47.42 | 43.90/44.80
3031 | 37.03/37.77 | 36.41/36.89
4341 | 36.21/37.57 | 36.13/36.51
168-3 | 8.89/ 9.65 | 8.81/ 9.79

SJR MVS 168-3 with high speed multiply
PGM= | 8.84 | 8.73
LOAD&GO | 9.3 | 9.1

also times approx;
145 168 91
145 SECS. 9.1 SECS 6.77 SECS

... snip ...


From: wheeler
Date: 02/20/79 09:12:59

Numbers fro Rain&Rain4 are virtual & total time (right off of CMS
ready message). Only diff. between rain&rain4 is one does a lot of
console output at intermediate steps. The job is fortran , extremely
heavy on floating point operations. It comes by the way of the palo
alto branch office. It was part of a bid proposal by the Lawrence
Radiation Lab. in Livermore (with specs that it used 35.77 cpu
secs. on a CDC6600).

VMA was turned on for all machines (but ECPS was not on the E4). The
CPU numbers are nearly the same on 168-3 for VM, MVS, & SVS (all using
FORTGI) so there is little operating system involved. (by the way,
from another source a comment was attributed to the same lab. that if
IBM had a 1 mip processor for under $300k, they would order 70 - thats
right seventy).

... snip ...

This appears to be a case where somebody that had seen my numbers and
had leaked them.

From: wheeler
Date: 02/26/79 17:56:35

has somebody else been doing a '1 fortran job' benchmark on the 4341?
Electronic news for Feb. 20, 1979 quotes an IBM spokesman as saying
based on 1 Fortran job, that it probably exceeds performance of a 3031
mainframe in running Fortran.

... snip ...

old posts mentioning rain/rain4
http://www.garlic.com/~lynn/2000d.html#0 Is a VAX a mainframe?
http://www.garlic.com/~lynn/2001d.html#67 Pentium 4 Prefetch engine?
http://www.garlic.com/~lynn/2002b.html#0 Microcode?
http://www.garlic.com/~lynn/2002e.html#75 Computers in Science Fiction
http://www.garlic.com/~lynn/2002i.html#7 CDC6600 - just how powerful a machine was it?
http://www.garlic.com/~lynn/2002i.html#12 CDC6600 - just how powerful a machine was it?
http://www.garlic.com/~lynn/2002i.html#19 CDC6600 - just how powerful a machine was it?
http://www.garlic.com/~lynn/2002i.html#22 CDC6600 - just how powerful a machine was it?
http://www.garlic.com/~lynn/2002k.html#4 misc. old benchmarks (4331 & 11/750)
http://www.garlic.com/~lynn/2003g.html#68 IBM zSeries in HPC
http://www.garlic.com/~lynn/2005m.html#25 IBM's mini computers--lack thereof
http://www.garlic.com/~lynn/2006x.html#31 The Future of CPUs: What's After Multi-Core?
Anne & Lynn Wheeler
2006-12-28 18:09:42 UTC
Permalink
Post by Anne & Lynn Wheeler
The 4341 tests were on an early endicott engineering machine
(delivered to disk test lab) that had some temporary patches that
slowed it down compared to what production machine would be.
re:
http://www.garlic.com/~lynn/2006y.html#21 moving on


i.e. "E4" was code name for 4341 ... production 4341 machine cycle
will be speeded up by about 15 percent (compared to E4 I was
benchmarking)

To: somebody in endicott
From: wheeler
Date: 01/22/79 19:22:21

Do you know anybody knowledgeable about running VM on E4???
GPD test lab just got one, we gen'ed release 5 VM to run on it. It
seems to work alright, except the E4 seems to have some hardware
(red lighting) problem with the interval timer. Hopefully that
will be corrected shortly.

... snip ...

From: wheeler
Date: 01/23/79 13:30:07

I sent a message to Endicott saying that we had IPL'ed release 5 on
the E4 and asking if anybody knew of any problems we would run into
using release 5. I also mentioned that it red lighted when we 1st
IPL'ed.

Endicott is now trying to answer the red light question. I got a call
from XXXXX who designed it, asking questions and offering suggestions.
He is calling YYYYY now to see if he can help any. It seems to have
gotten a lot more complex than i had thot.

... snip ...

From: wheeler
Date: 01/23/79 15:39:46

Just tried Q SRM DSPSL on E4 , it comes out 23.5 compared to 24.1 on 3031
and 26.1 on a 158-3.

Engineers said this is early model with 'slow' internal clock. Clock
will be speeded up at least by 1/7 which would bring DSPSL down to
20.0 or a little below. Box looks like an old fashion Freezer chest,
only about 12 inches higher and 50 % longer.

... snip ...
Anne & Lynn Wheeler
2006-12-29 19:31:23 UTC
Permalink
Post by Anne & Lynn Wheeler
For relocate shared segment support, a shared segment may appear
anywhere within a virtual machine's address space (it does not need to
be at the position specified in the VMABLOK). The way I handled it in
DMKVMA was to use the PTO pointers in the VMABLOK to check the shared
segments, rather than using the segment index number to displace into
the segment table and pick-up the STE.
One of the co-op students that helped me write the original shared
segment support for release 2 VM (included the sub-set that is now in
the product DCSS) is now with Interactive Data Corporation (IDC). They
have taken the idea and put a whole group on expanding the idea. They
now call it Floating segments (instead of relocating segments). They
have a modified assembler for generating adcon free code and are
working on the compilers. All this work they have done has greater
significance than they realize. It would greatly simplify conversion
to an increased address space size.
re:
http://www.garlic.com/~lynn/2006y.html#20 moving on
and specifically the old email
http://www.garlic.com/~lynn/2006y.html#email790326
and other posts in this thread
http://www.garlic.com/~lynn/2006y.html#21 moving on
http://www.garlic.com/~lynn/2006y.html#23 moving on

one of the big problems was that the original 370 virtual memory
architecture included "segment protect" feature (i.e. turn on a bit in
segment table entry for a specific virtual address space ... and
everything in that segment became read/only for that address space).

the cp67 to vm370 morph of cms was somewhat structured around having
that feature. i've posted before how the retrofit of virtual memory
hardware to 370/165 ran into schedule problems and they dropped a
number of features from the 370 virtual memory architecture to buy
back six months in the schedule (and then made all other processors
drop them also so that there was compatibility across the 370 line).

this resulted in forcing vm370 to revert to the cp67 convention of
protecting shared pages ... which played games with storage protect
keys. this resulted in addition vm370 overhead for cms ... but a
little later also met than VMA (virtual machine assist) microcode
performance enhancements couldn't be used with shared-system CMS (VMA
implemenation of storage key operations didn't know the rules for
protecting shared segment pages).

preparing for vm370 release 3 ... somebody came up with a hack that
would allow VMA to be used with CMS ... the storage key game was
eliminated and instead the currently running CMS would be allowed to
modify shared pages (as well as being able to run with VMA turned
on). however before switching to a different process, the dispatcher
would scan all shared pages ... searching for ones that had been
changed. If any were found ... they were discarded (new process
requiring discarded shared page would have an unmodified copy
refreshed from disk). The trade-off of reduced overhead being able to
use VMA tended to offset the increased overhead that the dispatcher
had to scan 16 shared pages on (nearly) every process switch.

then it was dediced to pick up a very small subset of my virtual
memory management support (both cp and cms changes) as "DCSS" for
release 3
http://www.garlic.com/~lynn/subtopic.html#mmap
http://www.garlic.com/~lynn/subtopic.html#adcon

this initially resulted in at least doubling the typical number of
shared pages from 16 to 32. However, the overhead of the dispatcher
scanning of 32 shared pages (on every process switch) changed the
overhead trade-off vis-a-vis overhead reduction being able to use
VMA. Somebody then decided they had to go with the change page
scanning hack anyway ... since CMS intensive customers had already
been told that they would get performance benefit in vm370 release 3
with using VMA.

This was further aggrevated when developing multiprocessor support
that would be shipped in vm370 release 4. The change in release 3 for
scanning for changed shared pages was predicated on a single process
having exclusive access to the shared pages at a time. With
multi-processer support, there could be multiple, concurrent running
processes. To preserve the "exclusive access" assumption, it was then
necessary to have processor specific copies of shared pages. Now, not
only did the dispatcher have to scan (and increasing number of) shared
pages for changes (on nearly every task switch) ... but it also had to
make sure that the "switched-to" process had its (virtual address)
segment table entries pointed to the processor specific shared
segments. Now, things were getting entirely out of control.

Another issue that had come up was that the original relational/sql,
system/r had been developed on vm370 and was taking advantage of more
sophisticated virtual memory support. One of the things allowed some
processes address spaces to have r/w shared access to a shared
segments while other processes had only r/o shared access
http://www.garlic.com/~lynn/subtopic.html#systemr
it was referred to as "DWSS" in the technology transfer effort from
SJR to Endicott for what became SQL/DS. few recent posts mentioning
DWSS
http://www.garlic.com/~lynn/2006t.html#16 Is the teaching of non-reentrant HLASM coding practices ever defensible?
http://www.garlic.com/~lynn/2006t.html#39 Why these original FORTRAN quirks?
http://www.garlic.com/~lynn/2006w.html#11 long ago and far away, vm370 from early/mid 70s

Futhermore, the processing load on the US HONE system was increasing
and they were upgrading their 370/168s to multiprocessors ... HONE was
vm370 based infrastructure that provided world-wide support to
marketing, sales, and field people.
http://www.garlic.com/~lynn/subtopic.html#hone

HONE was doing this 6-9 months before release 4 (and official
multiprocessor support) was going to be available.

As i had been involved in a lot of the multiprocessor support
http://www.garlic.com/~lynn/subtopic.html#smp
http://www.garlic.com/~lynn/subtopic.html#bounce

I undertook to build a version of multiprocessor support on their
production vm370 release 3 (which I had heavily modified already).
While, I was doing that, I went ahead and put in the code to revert to
protection games with storage keys (eliminating having to have unique
shared page copies for every processor) that had existing in cp67 and
in vm370 prior to release 3.

for a little drift, pieces of recent thread in comp.arch on virtual
address space mappings
http://www.garlic.com/~lynn/2006w.html#23 Multiple mappings
http://www.garlic.com/~lynn/2006x.html#23 Multiple mappings
http://www.garlic.com/~lynn/2006x.html#26 Multiple mappings
http://www.garlic.com/~lynn/2006y.html#11 Multiple mappings

past posts mentioning problem/issues retrofitting virtual memory
support to 370/165
http://www.garlic.com/~lynn/2000d.html#82 "all-out" vs less aggressive designs (was: Re: 36 to 32 bit transition)
http://www.garlic.com/~lynn/2000f.html#35 Why IBM use 31 bit addressing not 32 bit?
http://www.garlic.com/~lynn/2000f.html#55 X86 ultimate CISC? No. (was: Re: "all-out" vs less aggressive designs)
http://www.garlic.com/~lynn/2000f.html#63 TSS ancient history, was X86 ultimate CISC? designs)
http://www.garlic.com/~lynn/2000g.html#10 360/370 instruction cycle time
http://www.garlic.com/~lynn/2000g.html#15 360/370 instruction cycle time
http://www.garlic.com/~lynn/2000g.html#16 360/370 instruction cycle time
http://www.garlic.com/~lynn/2000g.html#21 360/370 instruction cycle time
http://www.garlic.com/~lynn/2001.html#63 Are the L1 and L2 caches flushed on a page fault ?
http://www.garlic.com/~lynn/2001b.html#37 John Mashey's greatest hits
http://www.garlic.com/~lynn/2001c.html#7 LINUS for S/390
http://www.garlic.com/~lynn/2001k.html#8 Minimalist design (was Re: Parity - why even or odd)
http://www.garlic.com/~lynn/2002.html#48 Microcode?
http://www.garlic.com/~lynn/2002.html#50 Microcode?
http://www.garlic.com/~lynn/2002.html#52 Microcode?
http://www.garlic.com/~lynn/2002g.html#47 Why are Mainframe Computers really still in use at all?
http://www.garlic.com/~lynn/2002l.html#51 Handling variable page sizes?
http://www.garlic.com/~lynn/2002m.html#2 Handling variable page sizes?
http://www.garlic.com/~lynn/2002m.html#68 Tweaking old computers?
http://www.garlic.com/~lynn/2002n.html#10 Coherent TLBs
http://www.garlic.com/~lynn/2002n.html#15 Tweaking old computers?
http://www.garlic.com/~lynn/2002n.html#23 Tweaking old computers?
http://www.garlic.com/~lynn/2002n.html#32 why does wait state exist?
http://www.garlic.com/~lynn/2002n.html#58 IBM S/370-168, 195, and 3033
http://www.garlic.com/~lynn/2002p.html#44 Linux paging
http://www.garlic.com/~lynn/2003e.html#12 Resolved: There Are No Programs With >32 Bits of Text
http://www.garlic.com/~lynn/2003f.html#56 ECPS:VM DISPx instructions
http://www.garlic.com/~lynn/2003g.html#19 Multiple layers of virtual address translation
http://www.garlic.com/~lynn/2003g.html#20 price ov IBM virtual address box??
http://www.garlic.com/~lynn/2003h.html#37 Does PowerPC 970 has Tagged TLBs (Address Space Identifiers)
http://www.garlic.com/~lynn/2003m.html#34 SR 15,15 was: IEFBR14 Problems
http://www.garlic.com/~lynn/2003m.html#37 S/360 undocumented instructions?
http://www.garlic.com/~lynn/2004c.html#6 If the x86 ISA could be redone
http://www.garlic.com/~lynn/2004p.html#8 vm/370 smp support and shared segment protection hack
http://www.garlic.com/~lynn/2005b.html#53 The mid-seventies SHARE survey
http://www.garlic.com/~lynn/2005b.html#62 The mid-seventies SHARE survey
http://www.garlic.com/~lynn/2005e.html#53 System/360; Hardwired vs. Microcoded
http://www.garlic.com/~lynn/2005e.html#57 System/360; Hardwired vs. Microcoded
http://www.garlic.com/~lynn/2005e.html#59 System/360; Hardwired vs. Microcoded
http://www.garlic.com/~lynn/2005f.html#1 System/360; Hardwired vs. Microcoded
http://www.garlic.com/~lynn/2005f.html#45 Moving assembler programs above the line
http://www.garlic.com/~lynn/2005g.html#17 DOS/360: Forty years
http://www.garlic.com/~lynn/2005h.html#10 Exceptions at basic block boundaries
http://www.garlic.com/~lynn/2005h.html#18 Exceptions at basic block boundaries
http://www.garlic.com/~lynn/2005j.html#39 A second look at memory access alignment
http://www.garlic.com/~lynn/2005p.html#45 HASP/ASP JES/JES2/JES3
http://www.garlic.com/~lynn/2005r.html#51 winscape?
http://www.garlic.com/~lynn/2005s.html#23 winscape?
http://www.garlic.com/~lynn/2006.html#13 VM maclib reference
http://www.garlic.com/~lynn/2006.html#38 Is VIO mandatory?
http://www.garlic.com/~lynn/2006e.html#0 About TLB in lower-level caches
http://www.garlic.com/~lynn/2006e.html#5 About TLB in lower-level caches
http://www.garlic.com/~lynn/2006e.html#12 About TLB in lower-level caches
http://www.garlic.com/~lynn/2006e.html#46 using 3390 mod-9s
http://www.garlic.com/~lynn/2006i.html#4 Mainframe vs. xSeries
http://www.garlic.com/~lynn/2006i.html#9 Hadware Support for Protection Bits: what does it really mean?
http://www.garlic.com/~lynn/2006i.html#23 Virtual memory implementation in S/370
http://www.garlic.com/~lynn/2006j.html#5 virtual memory
http://www.garlic.com/~lynn/2006j.html#31 virtual memory
http://www.garlic.com/~lynn/2006j.html#41 virtual memory
http://www.garlic.com/~lynn/2006k.html#57 virtual memory
http://www.garlic.com/~lynn/2006l.html#22 Virtual Virtualizers
http://www.garlic.com/~lynn/2006m.html#26 Mainframe Limericks
http://www.garlic.com/~lynn/2006n.html#16 On the 370/165 and the 360/85
http://www.garlic.com/~lynn/2006r.html#36 REAL memory column in SDSF
http://www.garlic.com/~lynn/2006s.html#30 Why magnetic drums was/are worse than disks ?
http://www.garlic.com/~lynn/2006s.html#61 Is the teaching of non-reentrant HLASM coding practices ever defensible?
http://www.garlic.com/~lynn/2006t.html#1 Is the teaching of non-reentrant HLASM coding practices ever
http://www.garlic.com/~lynn/2006u.html#60 Why these original FORTRAN quirks?
http://www.garlic.com/~lynn/95.html#3 What is an IBM 137/148 ???
http://www.garlic.com/~lynn/99.html#7 IBM S/360
http://www.garlic.com/~lynn/99.html#204 Core (word usage) was anti-equipment etc
http://www.garlic.com/~lynn/99.html#209 Core (word usage) was anti-equipment etc
Anne & Lynn Wheeler
2007-01-02 20:04:17 UTC
Permalink
Post by Anne & Lynn Wheeler
For relocate shared segment support, a shared segment may appear
anywhere within a virtual machine's address space (it does not need to
be at the position specified in the VMABLOK). The way I handled it in
DMKVMA was to use the PTO pointers in the VMABLOK to check the shared
segments, rather than using the segment index number to displace into
the segment table and pick-up the STE.
One of the co-op students that helped me write the original shared
segment support for release 2 VM (included the sub-set that is now in
the product DCSS) is now with Interactive Data Corporation (IDC). They
have taken the idea and put a whole group on expanding the idea. They
now call it Floating segments (instead of relocating segments). They
have a modified assembler for generating adcon free code and are
working on the compilers. All this work they have done has greater
significance than they realize. It would greatly simplify conversion
to an increased address space size.
re:
http://www.garlic.com/~lynn/2006y.html#20 moving on
http://www.garlic.com/~lynn/2006y.html#21 moving on
http://www.garlic.com/~lynn/2006y.html#23 moving on
http://www.garlic.com/~lynn/2006y.html#26 moving on

"XXXXXX" was one of the two original people at the Los Gatos lab.
responsible for mainframe pascal. He went on to be vp of
software development at MIPs and later showed up as general
manager of the SUN business unit responsible for the fledgling
JAVA.

misc. collected posts about difficulty with positioning
executables (that followed standard os/360 conventions)
http://www.garlic.com/~lynn/subtopic.html#adcon

From: wheeler
Date: 10/08/80 16:51:57

re: relocating shared code; XXXXXX thinks that he can have Pacal/VS
not using relative adcons and also "compile" code that doesn't have
relative adcons. Adcons are generated as absolute, the target address
minus the base address of the module. The loader supports both
positive and negative displacements. When it comes time to transfer
control the routine picks up the absolute adcon and adds in the value
of the base register to resolve the relocated address. Code can then
be generated in shared modules (ref: shared modules, RJ2928) and the
CMS loadmod upgraded to load code into available segments (of course
the same procedure works for non-shared modules also).

... snip ...

other references to mips/sun things long ago and far away:
http://www.garlic.com/~lynn/2000.html#15 Computer of the century
http://www.garlic.com/~lynn/2004c.html#25 More complex operations now a better choice?
http://www.garlic.com/~lynn/2004q.html#35 [Lit.] Buffer overruns
http://www.garlic.com/~lynn/2005b.html#14 something like a CTC on a PC
http://www.garlic.com/~lynn/2005r.html#20 Intel strikes back with a parallel x86 design
http://www.garlic.com/~lynn/2006u.html#31 To RISC or not to RISC
Anne & Lynn Wheeler
2007-01-12 15:43:30 UTC
Permalink
Just for my curiousity. Was CP-67 the first "virtualization engine" ever
produced? Or did some other company have this type of ability before IBM
did it?
cp40 predated cp67.

the science center really wanted a 360/50 to modify for virtual memory ... but all of the spare 50s were going to the FAA ... so they had to settle for 360/40. when 360/67 finally became available they ported cp40 to cp67. lots of posts mentioning the science center
http://www.garlic.com/~lynn/subtopic.html#545tech

recent post mentioning some wiki entries about cp/cms
http://www.garlic.com/~lynn/2007.html#8 "The Elements of Programming Style"
http://www.garlic.com/~lynn/2007.html#12 "The Elements of Programming Style"

a couple other posts in that thread
http://www.garlic.com/~lynn/2006y.html#20 "The Elements of Programming Style"
http://www.garlic.com/~lynn/2006y.html#34 "The Elements of Programming Style"
http://www.garlic.com/~lynn/2007.html#1 "The Elements of Programming Style"

not the 60s ... but index of old email (mostly from the 70s and 80s), much
of it vm related
http://www.garlic.com/~lynn/lhwemail.html

=====

and large number of past posts mentioning cp40
http://www.garlic.com/~lynn/93.html#0 360/67, was Re: IBM's Project F/S ?
http://www.garlic.com/~lynn/93.html#23 MTS & LLMPS?
http://www.garlic.com/~lynn/93.html#25 MTS & LLMPS?
http://www.garlic.com/~lynn/94.html#37 SIE instruction (S/390)
http://www.garlic.com/~lynn/94.html#46 Rethinking Virtual Memory
http://www.garlic.com/~lynn/94.html#53 How Do the Old Mainframes
http://www.garlic.com/~lynn/94.html#54 How Do the Old Mainframes
http://www.garlic.com/~lynn/97.html#22 Pre S/360 IBM Operating Systems?
http://www.garlic.com/~lynn/98.html#28 Drive letters
http://www.garlic.com/~lynn/98.html#33 ... cics ... from posting from another list
http://www.garlic.com/~lynn/98.html#45 Why can't more CPUs virtualize themselves?
http://www.garlic.com/~lynn/99.html#126 Dispute about Internet's origins
http://www.garlic.com/~lynn/99.html#139 OS/360 (and descendents) VM system?
http://www.garlic.com/~lynn/99.html#142 OS/360 (and descendents) VM system?
http://www.garlic.com/~lynn/99.html#174 S/360 history
http://www.garlic.com/~lynn/99.html#237 I can't believe this newsgroup still exists
http://www.garlic.com/~lynn/2000.html#52 Correct usage of "Image" ???
http://www.garlic.com/~lynn/2000.html#81 Ux's good points.
http://www.garlic.com/~lynn/2000.html#82 Ux's good points.
http://www.garlic.com/~lynn/2000c.html#42 Domainatrix - the final word
http://www.garlic.com/~lynn/2000c.html#79 Unisys vs IBM mainframe comparisons
http://www.garlic.com/~lynn/2000e.html#16 First OS with 'User' concept?
http://www.garlic.com/~lynn/2000f.html#30 OT?
http://www.garlic.com/~lynn/2000f.html#59 360 Architecture, Multics, ... was (Re: X86 ultimate CISC? No.)
http://www.garlic.com/~lynn/2000f.html#63 TSS ancient history, was X86 ultimate CISC? designs)
http://www.garlic.com/~lynn/2000f.html#66 360 Architecture, Multics, ... was (Re: X86 ultimate CISC? No.)
http://www.garlic.com/~lynn/2000f.html#78 TSS ancient history, was X86 ultimate CISC? designs)
http://www.garlic.com/~lynn/2001b.html#29 z900 and Virtual Machine Theory
http://www.garlic.com/~lynn/2001h.html#9 VM: checking some myths.
http://www.garlic.com/~lynn/2001h.html#10 VM: checking some myths.
http://www.garlic.com/~lynn/2001h.html#46 Whom Do Programmers Admire Now???
http://www.garlic.com/~lynn/2001i.html#34 IBM OS Timeline?
http://www.garlic.com/~lynn/2001i.html#39 IBM OS Timeline?
http://www.garlic.com/~lynn/2001m.html#47 TSS/360
http://www.garlic.com/~lynn/2001m.html#49 TSS/360
http://www.garlic.com/~lynn/2002b.html#6 Microcode?
http://www.garlic.com/~lynn/2002b.html#44 PDP-10 Archive migration plan
http://www.garlic.com/~lynn/2002b.html#64 ... the need for a Museum of Computer Software
http://www.garlic.com/~lynn/2002c.html#8 TOPS-10 logins (Was Re: HP-2000F - want to know more about it)
http://www.garlic.com/~lynn/2002c.html#39 VAX, M68K complex instructions (was Re: Did Intel Bite Off More Than It Can Chew?)
http://www.garlic.com/~lynn/2002c.html#44 cp/67 (coss-post warning)
http://www.garlic.com/~lynn/2002e.html#47 Multics_Security
http://www.garlic.com/~lynn/2002f.html#30 Computers in Science Fiction
http://www.garlic.com/~lynn/2002f.html#36 Blade architectures
http://www.garlic.com/~lynn/2002g.html#13 Secure Device Drivers
http://www.garlic.com/~lynn/2002h.html#59 history of CMS
http://www.garlic.com/~lynn/2002h.html#62 history of CMS
http://www.garlic.com/~lynn/2002h.html#70 history of CMS
http://www.garlic.com/~lynn/2002j.html#64 vm marketing (cross post)
http://www.garlic.com/~lynn/2002l.html#22 Computer Architectures
http://www.garlic.com/~lynn/2002l.html#56 10 choices that were critical to the Net's success
http://www.garlic.com/~lynn/2002l.html#65 The problem with installable operating systems
http://www.garlic.com/~lynn/2002m.html#3 The problem with installable operating systems
http://www.garlic.com/~lynn/2002n.html#28 why does wait state exist?
http://www.garlic.com/~lynn/2003b.html#0 Disk drives as commodities. Was Re: Yamhill
http://www.garlic.com/~lynn/2003b.html#44 filesystem structure, was tape format (long post)
http://www.garlic.com/~lynn/2003f.html#2 History of project maintenance tools -- what and when?
http://www.garlic.com/~lynn/2003g.html#31 Lisp Machines
http://www.garlic.com/~lynn/2003g.html#33 price ov IBM virtual address box??
http://www.garlic.com/~lynn/2003k.html#5 What is timesharing, anyway?
http://www.garlic.com/~lynn/2003k.html#9 What is timesharing, anyway?
http://www.garlic.com/~lynn/2003k.html#24 Microkernels are not "all or nothing". Re: Multics Concepts For
http://www.garlic.com/~lynn/2003k.html#48 Who said DAT?
http://www.garlic.com/~lynn/2003m.html#4 IBM Manuals from the 1940's and 1950's
http://www.garlic.com/~lynn/2003m.html#16 OSI not quite dead yet
http://www.garlic.com/~lynn/2003m.html#31 SR 15,15 was: IEFBR14 Problems
http://www.garlic.com/~lynn/2003m.html#34 SR 15,15 was: IEFBR14 Problems
http://www.garlic.com/~lynn/2003m.html#36 S/360 undocumented instructions?
http://www.garlic.com/~lynn/2003o.html#32 who invented the "popup" ?
http://www.garlic.com/~lynn/2003o.html#47 Funny Micro$oft patent
http://www.garlic.com/~lynn/2004.html#45 40th anniversary of IBM System/360 on 7 Apr 2004
http://www.garlic.com/~lynn/2004b.html#0 Is DOS unix?
http://www.garlic.com/~lynn/2004c.html#11 40yrs, science center, feb. 1964
http://www.garlic.com/~lynn/2004c.html#25 More complex operations now a better choice?
http://www.garlic.com/~lynn/2004f.html#17 IBM 7094 Emulator - An historic moment?
http://www.garlic.com/~lynn/2004f.html#63 before execution does it require whole program 2 b loaded in
http://www.garlic.com/~lynn/2004g.html#4 Infiniband - practicalities for small clusters
http://www.garlic.com/~lynn/2004g.html#48 Hercules
http://www.garlic.com/~lynn/2004h.html#29 BLKSIZE question
http://www.garlic.com/~lynn/2004h.html#34 Which Monitor Would You Pick??????
http://www.garlic.com/~lynn/2004m.html#7 Whatever happened to IBM's VM PC software?
http://www.garlic.com/~lynn/2004n.html#3 Shipwrecks
http://www.garlic.com/~lynn/2004n.html#4 RISCs too close to hardware?
http://www.garlic.com/~lynn/2004n.html#25 Shipwrecks
http://www.garlic.com/~lynn/2005c.html#56 intel's Vanderpool and virtualization in general
http://www.garlic.com/~lynn/2005e.html#57 System/360; Hardwired vs. Microcoded
http://www.garlic.com/~lynn/2005f.html#10 Where should the type information be: in tags and descriptors
http://www.garlic.com/~lynn/2005o.html#4 Robert Creasy, RIP
http://www.garlic.com/~lynn/2005s.html#21 MVCIN instruction
http://www.garlic.com/~lynn/2005s.html#23 winscape?
http://www.garlic.com/~lynn/2005u.html#47 The rise of the virtual machines
http://www.garlic.com/~lynn/2006.html#34 UMA vs SMP? Clarification of terminology
http://www.garlic.com/~lynn/2006c.html#18 Change in computers as a hobbiest
http://www.garlic.com/~lynn/2006i.html#22 virtual memory
http://www.garlic.com/~lynn/2006i.html#30 virtual memory
http://www.garlic.com/~lynn/2006i.html#31 virtual memory
http://www.garlic.com/~lynn/2006i.html#32 virtual memory
http://www.garlic.com/~lynn/2006j.html#29 How to implement Lpars within Linux
http://www.garlic.com/~lynn/2006k.html#30 PDP-1
http://www.garlic.com/~lynn/2006k.html#41 PDP-1
http://www.garlic.com/~lynn/2006l.html#16 virtual memory
http://www.garlic.com/~lynn/2006m.html#25 Mainframe Limericks
http://www.garlic.com/~lynn/2006m.html#42 Why Didn't The Cent Sign or the Exclamation Mark Print?
http://www.garlic.com/~lynn/2006o.html#27 oops
http://www.garlic.com/~lynn/2006o.html#29 oops, cics
http://www.garlic.com/~lynn/2006s.html#21 Very slow booting and running and brain-dead OS's?
http://www.garlic.com/~lynn/2006s.html#65 Paranoia..Paranoia..Am I on the right track?.. any help please?
http://www.garlic.com/~lynn/2006t.html#23 threads versus task
http://www.garlic.com/~lynn/2006w.html#22 Are hypervisors the new foundation for system software?
http://www.garlic.com/~lynn/2006x.html#23 Multiple mappings

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